DocumentCode
1443453
Title
Power Supply Noise: A Survey on Effects and Research
Author
Tehranipoor, Mohammad ; Butler, Kenneth M.
Author_Institution
Univ. of Connecticut, Storrs, CT, USA
Volume
27
Issue
2
fYear
2010
Firstpage
51
Lastpage
67
Abstract
As technology scales to 32 nm and functional frequency and density continue to rise, PSN effects, which can reduce a circuit´s noise immunity and could lead to failures, pose new challenges to chip manufacturers and foundries. This article provides an overview of low-power and delay testing, and surveys ongoing research for analyzing and dealing with PSN effects during delay test and timing analysis.
Keywords
power supply circuits; chip manufacturers; delay testing; low-power testing; power supply noise:; size 32 nm; timing analysis; Automatic test pattern generation; Circuit testing; Crosstalk; Delay effects; Frequency; Manufacturing; Power supplies; Semiconductor device noise; Test pattern generators; Timing; design and test; path delay testing; power supply noise (PSN); timing analysis; transition delay fault testing;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2010.52
Filename
5432323
Link To Document