Fin-Height Effect on Poly-Si/PVD-TiN Stacked-Gate FinFET Performance

Author

Hayashida, Tetsuro ; Endo, Kazuhiko ; Liu, Yongxun ; O´Uchi, Shin-Ichi ; Matsukawa, Takashi ; Mizubayashi, Wataru ; Migita, Shinji ; Morita, Yukinori ; Ota, Hiroyuki ; Hashiguchi, Hiroki ; Kosemura, Daisuke ; Kamei, Takahiro ; Tsukada, Junichi ; Ishikawa,

Author_Institution

Sch. of Sci. & Technol., Meiji Univ., Kawasaki, Japan

Volume

59

Issue

3

fYear

2012

fDate

3/1/2012 12:00:00 AM

Firstpage

647

Lastpage

653

Abstract

We compared the electrical characteristics, including mobility and on -state current I_on, of n⁺-poly-Si/PVD-TiN stacked-gate FinFETs with different fin heights H_fin. The mobility was enhanced in devices with taller fins due to increased tensile stress. However, as gate length Lg decreases, I_on for devices with tall fins becomes worse, probably due to a high parasitic resistance Rp. Furthermore, V_th variation increased with increasing H_fin due to rough etching of the fin sidewall. Process technologies for reducing Rp and etching technology that yields smooth precise profiles are essential to exploit the high performance of tall FinFETs.

Keywords

MOSFET; etching; silicon; titanium compounds; Si; TiN; fin sidewall; fin-height effect; parasitic resistance; poly-Si/PVD-TiN stacked-gate FinFET; rough etching; tensile stress; Educational institutions; Etching; FinFETs; Logic gates; Resistance; Silicon; Tin; FinFET; fin height; mobility; parasitic resistance titanium nitride (TiN);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2011.2181385

Filename

6148269