• DocumentCode
    1443912
  • Title

    Behavioral optimization using the manipulation of timing constraints

  • Author

    Potkonjak, Miodrag ; Srivastava, Mani

  • Author_Institution
    Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
  • Volume
    17
  • Issue
    10
  • fYear
    1998
  • fDate
    10/1/1998 12:00:00 AM
  • Firstpage
    936
  • Lastpage
    947
  • Abstract
    We introduce a transformation, named rephasing, that manipulates the timing parameters in control-data-flow graphs (CDFG´s) during the high-level synthesis of data-path-intensive applications. Timing parameters in such CDFG´s include the sample period, the latencies between input-output pairs, the relative times at which corresponding samples become available on different inputs, and the relative times at which the corresponding samples become available at the delay nodes. While some of the timing parameters may be constrained by performance requirements, or by the interface to the external world, others remain free to be chosen during the process of high-level synthesis. Traditionally high-level synthesis systems for data-path-intensive applications either have assumed that all the relative times, called phases, when corresponding samples are available at input and delay nodes are zero (i.e., all input and delay node samples enter at the initial cycle of the schedule) or have automatically assigned values to these phases as part of the data-path allocation/scheduling step in the case of newer schedulers that use techniques like overlapped scheduling to generate complex time shapes. Rephasing, however, manipulates the values of these phases as an algorithm transformation before the scheduling/allocation stage. The advantage of this approach is that phase values can be chosen to transform and optimize the algorithm for explicit metrics such as area, throughput, latency, and power. Moreover, the rephasing transformation can be combined with other transformations such as algebraic transformations. We have developed techniques for using rephasing to optimize a variety of design metrics, and our results show significant improvements in several design metrics. We have also investigated the relationship and interaction of rephasing with other high-level synthesis tasks
  • Keywords
    application specific integrated circuits; circuit optimisation; data flow graphs; delays; high level synthesis; timing; algebraic transformations; algorithm transformation; allocation; behavioral optimization; control-data-flow graphs; data-path-intensive applications; delay nodes; high-level synthesis; input-output pairs; latencies; latency; overlapped scheduling; phase values; rephasing; sample period; throughput; timing constraints; Algorithm design and analysis; Constraint optimization; Delay effects; Design optimization; Digital signal processing; High level synthesis; Scheduling algorithm; Signal processing algorithms; Throughput; Timing;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.728915
  • Filename
    728915