Circuit optimization using carry-save-adder cells

Author

Kim, Taewhan ; Jao, William ; Tjiang, Steve

Author_Institution

Dept. of Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea

Volume

17

Issue

10

fYear

1998

fDate

10/1/1998 12:00:00 AM

Firstpage

974

Lastpage

984

Abstract

Carry-save-adder (CSA) is the most often used type of operation in implementing a fast computation of arithmetics of register-transfer-level design in industry. This paper establishes a relationship between the properties of arithmetic computations and several optimizing transformations using CSAs to derive consistently better qualities of results than those of manual implementations. In particular, we introduce two important concepts, operation duplication and operation split, which are the main driving techniques of our algorithm for achieving an extensive utilization of CSAs. Experimental results from a set of typical arithmetic computations found in industry designs indicate that automating CSA optimization with our algorithm produces designs with up to 53% faster timing and up to 42% smaller area

Keywords

adders; carry logic; cellular arrays; circuit optimisation; high level synthesis; timing; area; arithmetic computations; carry-save-adder cells; circuit optimization; industry designs; operation duplication; operation split; optimizing transformations; register-transfer-level design; timing; Adders; Algorithm design and analysis; Arithmetic; Circuit optimization; Computer industry; Computer science; Design optimization; Industrial relations; Propagation delay; Timing;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.728918

Filename

728918