• DocumentCode
    1447120
  • Title

    Design of multipliers for GF(2m)

  • Author

    Mao, Zhi-Hong ; Shou, Guofa ; Hu, Ya ; Guo, Zhiyou

  • Author_Institution
    Sch. of Inf. & Commun. Eng., Beijing Univ. of Posts & Telecommun., Beijing, China
  • Volume
    46
  • Issue
    6
  • fYear
    2010
  • Firstpage
    419
  • Lastpage
    420
  • Abstract
    A new design of multipliers for GF(2m) based on combination of bit-serial and bit-parallel schemes with low complexity is proposed. Using pipeline architecture, the scheme yields significantly lower latency compared to known bit-parallel multipliers for GF(2m).
  • Keywords
    Galois fields; logic design; multiplying circuits; pipeline processing; Galois fields; bit-parallel multiplier; bit-serial multiplier; low complexity; pipeline architecture;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el.2010.0246
  • Filename
    5434621
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1447120