New clock-feedthrough compensation scheme for switched-current circuits

Author

Min, Byung-Moo ; Kim, Soo-Won

Author_Institution

Dept. of Electron. Eng., Korea Univ., Seoul, South Korea

Volume

45

Issue

11

fYear

1998

fDate

11/1/1998 12:00:00 AM

Firstpage

1508

Lastpage

1511

Abstract

An improved clock-feedthrough compensation scheme for switched current system is proposed. Both the signal dependent and the constant clock-feedthrough terms are canceled by using both nMOS and pMOS current samplers and by adopting a source replication technique. The proposed current memory cell was fabricated with 0.6 μm CMOS process. Both experimental and theoretical results on clock-feedthrough error reveal substantial reduction over the existing compensation schemes

Keywords

CMOS analogue integrated circuits; analogue processing circuits; analogue storage; error compensation; sampled data circuits; switched current circuits; timing; 0.6 micron; CMOS process; SI circuits; clock-feedthrough compensation scheme; clock-feedthrough error; constant clock-feedthrough terms; current memory cell; nMOS current samplers; pMOS current samplers; signal dependent terms; source replication technique; switched-current circuits; CMOS process; CMOS technology; Capacitance; Clocks; MOS devices; Sampled data systems; Signal processing; Switches; Switching circuits; Voltage;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.735364

Filename

735364