DocumentCode
1449317
Title
Early Analysis of Critical Faults: An Approach to Test Generation From Formal Specifications
Author
Das, Sourasis ; Banerjee, Ansuman ; Dasgupta, Pallab
Author_Institution
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Kharagpur, Kharagpur, India
Volume
31
Issue
3
fYear
2012
fDate
3/1/2012 12:00:00 AM
Firstpage
447
Lastpage
451
Abstract
This paper presents a formal methodology for test generation from formal specifications. Our method can be used for test generation for critical faults in component-based designs. Test generation for critical faults is done entirely using formal specifications and therefore the theory inherently guarantees that a generated test will be applicable to any implementation of the specifications. The theory makes fault analysis possible at an abstract level of design where the complete logic is not specified.
Keywords
electronic engineering computing; fault diagnosis; formal specification; logic testing; critical fault; fault analysis; formal specification; test generation; Circuit faults; Computational modeling; Cost accounting; Fault tolerance; Fault tolerant systems; Integrated circuit modeling; Safety; Satisfiability; specification; test generation;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2011.2171183
Filename
6152773
Link To Document