A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/D converter

Author

Opris, Ion E. ; Lewicki, Laurence D. ; Wong, Bill C.

Author_Institution

SiPCore, Cupertino, CA, USA

Volume

33

Issue

12

fYear

1998

fDate

12/1/1998 12:00:00 AM

Firstpage

1898

Lastpage

1903

Abstract

This paper describes a fully monolithic 12-bit, 20 Msample/s, A/D converter. A power dissipation of 250 mW from a single 5 V supply is achieved using a radix=2 pipeline architecture. Linearity and full-scale errors are removed through self-calibration and digital correction with on-chip circuitry. A novel single-ended to differential sample and hold stage is proven to have very good single-ended input performance up to the Nyquist frequency. The total silicon area is 3.2×3.1 mm² in a 0.7 μm CMOS process. Several circuit techniques used in this design together with experimental results are presented

Keywords

CMOS integrated circuits; analogue-digital conversion; calibration; pipeline processing; switched capacitor networks; 0.7 micron; 12 bit; 250 mW; 5 V; CMOS process; Si; digital correction; monolithic ADC; pipeline A/D converter; pipeline architecture; sample/hold stage; self-calibrating ADC; single-ended ADC; CMOS technology; Capacitors; Circuits; Error correction; Feedback; Frequency; Linearity; Pipelines; Power dissipation; Throughput;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.735529

Filename

735529