A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

Author

Liu, Chun-Cheng ; Chang, Soon-Jyh ; Huang, Guan-Ying ; Lin, Ying-Zu

Author_Institution

Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan

Volume

45

Issue

4

fYear

2010

fDate

4/1/2010 12:00:00 AM

Firstpage

731

Lastpage

740

Abstract

This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the input common-mode voltage variation. The prototype was fabricated using 0.13-Â¿m 1P8M CMOS technology. At a 1.2-V supply and 50 MS/s, the ADC achieves an SNDR of 57.0 dB and consumes 0.826 mW, resulting in a figure of merit (FOM) of 29 fJ/conversion-step. The ADC core occupies an active area of only 195 Ã— 265 Â¿m².

Keywords

CMOS digital integrated circuits; analogue-digital conversion; capacitor switching; comparators (circuits); low-power electronics; CMOS technology; SAR ADC; SNDR; comparator; figure of merit; input common-mode voltage; low-power successive approximation register analog-to-digital converter; monotonic capacitor switching procedure; power 0.826 mW; signal-dependent offset; size 0.13 mum; voltage 1.2 V; word length 10 bit; Analog-digital conversion; CMOS process; CMOS technology; Capacitance; Capacitors; Energy consumption; Energy efficiency; Power dissipation; Sampling methods; Voltage; Analog-to-digital converter; energy efficient; low power; successive approximation register;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2010.2042254

Filename

5437496