Modeling modulators for A/D signal conversion

Author

Cho, Bylung Woog ; Hoi, Pyuny C. ; Sohn, Byuny Ki

Author_Institution

Sch. of Electron. & Electr. Eng., Kyungpook Nat. Univ., Taegu, South Korea

Volume

14

Issue

6

fYear

1998

fDate

11/1/1998 12:00:00 AM

Firstpage

26

Lastpage

31

Abstract

The performance of an SDM is reported to decline by various factors produced during the design and fabrication process. Namely, the nonideal factors are: the limit of the operational amplifier (op-amp) output swing, the finite DC gain of the op-amp, op-amp slew rate, the integrator gain error by mismatching of the capacitor and nonideality of the internal multibit quantizer. In this article we report not only modeling results of the ideal second-order SDM with a multibit quantizer, but also evaluate its performance according to bit number and OSR. In addition, we determine the maximum error limit of the SDM after investigating the influence of the nonideal factors on the performance of the SDM

Keywords

integrated circuit modelling; integrating circuits; operational amplifiers; quantisation (signal); sigma-delta modulation; A/D signal conversion; SDM; finite DC gain; integrator gain error; internal multibit quantizer; maximum error limit; multibit quantizer; nonideality; op-amp output swing; op-amp slew rate; Capacitors; Frequency; Mathematical model; Nonlinear distortion; Operational amplifiers; Resistors; Sampling methods; Signal processing; Signal sampling; Voltage;

fLanguage

English

Journal_Title

Circuits and Devices Magazine, IEEE

Publisher

ieee

ISSN

8755-3996

Type

jour

DOI

10.1109/101.735792

Filename

735792