A single-chip decoder for the POCSAG radiopaging code

Author

Drude, Stefan

Author_Institution

Philips Components, Hamburg, West Germany

Volume

36

Issue

4

fYear

1990

fDate

11/1/1990 12:00:00 AM

Firstpage

897

Lastpage

902

Abstract

An integrated low power consumption POCSAG (Post Office Code Standardization Advisory Group) decoder and pager controller circuit is described, and some information on the SAC-MOS (self-aligned contact CMOS) process used to manufacture it is given. The decoder implements digital filtering, clock recovery, synchronization, error detection and correction, and user interface functions. Since this IC has nonvolatile user address memory (EEPROM) on chip, only two integrated circuits are required to build a complete miniature alert-only pager. The characteristics of the decoder are summarized, and application examples are shown

Keywords

CMOS integrated circuits; codes; decoding; mobile radio systems; standardisation; EEPROM; IC; POCSAG radiopaging code; SAC-MOS process; alert-only pager; clock recovery; digital filtering; error correction; error detection; pager controller circuit; self-aligned contact CMOS; single-chip decoder; synchronization; user interface; CMOS memory circuits; CMOS process; Clocks; Decoding; Digital filters; Energy consumption; Filtering; Integrated circuit manufacture; Manufacturing processes; Standardization;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.61571

Filename

61571