Surface-states effects on GaAs FET electrical performance

Author

Ohno, Yasuo ; Francis, Pascale ; Nogome, Masanobu ; Takahashi, Yuji

Author_Institution

Opto-Electron. Res. Labs., NEC Corp., Ibaraki, Japan

Volume

46

Issue

1

fYear

1999

fDate

1/1/1999 12:00:00 AM

Firstpage

214

Lastpage

219

Abstract

We analyzed the effects of surface-states on GaAs FET electrical performance with a two-dimensional (2-D) device simulator that used a surface-state model based on Shockley-Read-Hall (SRH) statistics. We found that under typical FET operating conditions, electron-trap-type surface-states pin the surface potential to the electron quasi-Fermi level (that is, the n-type channel potential), whereas hole-trap-type surface-states pin it to the hole quasi-Fermi level (that is, the gate potential). This difference affects both the electric-field distribution along the channel and the drain current values. The transient responses to step-bias application at the gate and at the drain showed slow transients due to the surface-states, but the directions of the shifts were opposite for the different trap-types. We explain these phenomena using a theory based on Shockley-Read-Hall statistics for the surface-states

Keywords

Fermi level; III-V semiconductors; electron traps; field effect transistors; gallium arsenide; semiconductor device models; surface potential; surface states; GaAs; GaAs FET; Shockley-Read-Hall statistics; drain current; electric field; electrical performance; electron trap; quasi-Fermi level; surface potential; surface state model; transient response; two-dimensional device simulation; Analytical models; Charge carrier processes; Dielectric substrates; FETs; Frequency; Gallium arsenide; Laboratories; National electric code; Statistical analysis; Statistics;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.737461

Filename

737461