An electrical test structure for the measurement of planarization

Author

Elliott, Jane P. ; Fallon, Martin ; Walton, Anthony J. ; Stevenson, J.T.M. ; O´Hara, Anthony ; Gundlach, Alan M.

Author_Institution

Dept. of Electr. Eng., Edinburgh Univ., UK

Volume

10

Issue

2

fYear

1997

fDate

5/1/1997 12:00:00 AM

Firstpage

242

Lastpage

249

Abstract

This paper presents the simulation and experimental measurements of an electrical test structure that can be used to assess the degree of planarization of interlayer dielectrics. It consists of two sets of metal combs separated by a dielectric. For each structure the combs on the two layers overlap each other, with adjacent structures having the overlap in one direction progressionally offset by 0.2 μm. The capacitance of these structures is then measured, from which the degree of planarization can be assessed. This structure has potential applications for characterising chemical mechanical polishing (CMP) processes for multilevel very large scale integration (VLSI) applications

Keywords

VLSI; capacitance measurement; dielectric thin films; integrated circuit interconnections; integrated circuit measurement; integrated circuit metallisation; integrated circuit testing; surface topography measurement; CMP process characterisation; capacitance; chemical mechanical polishing processes; electrical test structure; interlayer dielectrics; metal combs; multilevel VLSI applications; planarization measurement; Chemical technology; Dielectric measurements; Electric variables measurement; Integrated circuit interconnections; Metallization; Parasitic capacitance; Planarization; Surface topography; Testing; Very large scale integration;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.572076

Filename

572076