A novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques

Author

Liu, S.C. ; Wu, F.A. ; Kuo, James B.

Author_Institution

Nat. Taiwan Univ., Taipei, Taiwan

Volume

36

Issue

4

fYear

2001

fDate

4/1/2001 12:00:00 AM

Firstpage

712

Lastpage

716

Abstract

This paper reports a novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques. With two auxiliary pass transistors to dynamically control the bodies of transistors in the tag-compare portion of CAM cell, this SOI CAM cell has a fast tag-compare capability at a low supply voltage of 0.7 V as verified by the results from the two-dimensional semiconductor device simulation program MEDICI

Keywords

CMOS analogue integrated circuits; CMOS memory circuits; VLSI; content-addressable storage; integrated circuit modelling; low-power electronics; silicon-on-insulator; 0.7 V; 2D semiconductor device simulation program; MEDICI; SRAM cell portion; VLSI; fast tag-compare capability; low-voltage content-addressable-memory cell; partially depleted SOI CMOS dynamic-threshold; transient analysis; two auxiliary pass transistors; CADCAM; CMOS technology; Circuits; Computer aided manufacturing; Logic; Low voltage; Random access memory; Semiconductor devices; Very large scale integration; Voltage control;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.913752

Filename

913752