DocumentCode
1461503
Title
Design of Microstrip-to-Microstrip Via Transition in Multilayered LTCC for Frequencies up to 67 GHz
Author
Tsai, Chih-Chun ; Cheng, Yung-Shou ; Huang, Ting-Yi ; Hsu, Yungping Alvin ; Wu, Ruey-Beei
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
1
Issue
4
fYear
2011
fDate
4/1/2011 12:00:00 AM
Firstpage
595
Lastpage
601
Abstract
A wide-band microstrip-to-microstrip via transition proposed for connecting an integrated circuit chip and an antenna array on the opposite sides of a multilayered low-temperature co-fired ceramic substrate is investigated in this paper. To facilitate the design, it is decomposed into external and internal segments, which consist of two microstrip-to-via transitions and a multilayered through-hole via with four ground vias, respectively. The equivalent impedance of the internal segment is carefully calculated from the lump-circuit model extracted by Ansoft Q3D, and verified by high-frequency structure simulation (HFSS). The S-parameters of external segments are simulated by HFSS for impedance matching, thereby obtaining the appropriate physical parameters. The physical mechanisms that result in the insertion loss are explored in detail, and the effects of via diameter are also investigated for the reduction of insertion loss. By combining the designs of the external and internal segments, the simulated S-parameters demonstrated that the overall return loss level was above 20 dB within 57-67 GHz spectrum and insertion loss was better than 0.48 dB from d.c. up to 67 GHz. Coherent results between simulation and measurement were also obtained with a back-to-back transition structure.
Keywords
S-parameters; antenna arrays; ceramics; impedance matching; integrated circuit interconnections; microstrip transitions; Ansoft Q3D; HFSS; S-parameters; antenna array; back-to-back transition structure; equivalent impedance; external segments; ground vias; high-frequency structure simulation; impedance matching; insertion loss reduction; integrated circuit chip; internal segments; lump-circuit model; microstrip-to-via transitions; multilayered LTCC; multilayered low-temperature co-fired ceramic substrate; multilayered through-hole via; overall return loss level; physical mechanisms; via diameter; wide-band microstrip-to-microstrip via transition; Capacitance; Conductors; Dielectric losses; Insertion loss; Microstrip; Scattering parameters; Low temperature co-fired ceramic; multilayered; via transition; wide-band interconnects;
fLanguage
English
Journal_Title
Components, Packaging and Manufacturing Technology, IEEE Transactions on
Publisher
ieee
ISSN
2156-3950
Type
jour
DOI
10.1109/TCPMT.2011.2104416
Filename
5721794
Link To Document