DocumentCode
146214
Title
Power aware parallel computing on asymmetric multiprocessor
Author
Manakkadu, Sheheeda ; Dutta, Suparna ; Botros, Nazeih M.
Author_Institution
Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
fYear
2014
fDate
2-5 Sept. 2014
Firstpage
35
Lastpage
40
Abstract
Power optimization of multi-threaded parallel applications is necessary to achieve good performance on multi-core processors while saving power. Certain threads wait for other threads due to synchronization. These threads are critical in full program performance. Identifying these threads can reveal power optimization opportunities for software and hardware designers. In this paper, we propose a metric to determine critical threads. Our proposed method combines Instructions Per Cycle (IPC) of a thread and sum of IPCs of all co-running threads within a time quanta. We present a low power hardware based technique to calculate scores in order to determine critical threads. We use our score metric to create stacks that break total execution time into each thread´s score components which makes it visually easier to determine optimization opportunities. Asymmetric multiprocessors have been proposed to scale the frequency by exploiting the stacks to achieve power optimization without losing much performance. To validate our proposed method, we used gem5 simulator to design an asymmetric multi-core processor and performed different multi-threaded parallel applications from the SPLASH2 benchmark. By applying asymmetric frequency scaling directed by our proposed metric, we achieved 28.13% savings in average power consumption with a maximum of 7.1% performance loss.
Keywords
multi-threading; parallel processing; power aware computing; IPC; SPLASH2 benchmark; asymmetric frequency scaling; asymmetric multicore processor; asymmetric multiprocessors; critical threads; gem5 simulator; hardware designer; instructions per cycle; low power hardware based technique; multicore processors; multithreaded parallel applications; power aware parallel computing; power optimization opportunities; power saving; software designer; thread score components; Hardware; Instruction sets; Multicore processing; Optimization; Synchronization;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip Conference (SOCC), 2014 27th IEEE International
Conference_Location
Las Vegas, NV
Type
conf
DOI
10.1109/SOCC.2014.6948896
Filename
6948896
Link To Document