• DocumentCode
    1464664
  • Title

    Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain extension

  • Author

    Lin, H.C. ; Yeh, K.-L. ; Huang, R.G. ; Lin, C.Y. ; Huang, T.Y.

  • Author_Institution
    Nat. Nano Device Labs., Hsinchu, Taiwan
  • Volume
    22
  • Issue
    4
  • fYear
    2001
  • fDate
    4/1/2001 12:00:00 AM
  • Firstpage
    179
  • Lastpage
    181
  • Abstract
    A novel Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain (FID) extension is proposed and demonstrated. In the new device configuration, a metal field-plate (or sub-gate) lying on the passivation oxide is employed to induce a sheet of carriers in a channel offset region located between the silicided drain and the active channel region underneath the main gate. The new device thus allows ambipolar device operation by simply switching the polarity of the bias applied to the field plate. In contrast to the conventional SBTFT that suffers from high GIDL (gate-induced drain leakage)-like off-state leakage current, the new SBTFT with FID is essentially free from the GIDL-like leakage current. In addition, unlike the conventional SBTFT that suffers from low on-off current ratio, the new device exhibits high on/off current ratio up to 10/sup 6/ for both n- and p-channel modes of operation. Moreover, the implantless feature and the ambipolar capability of the new device also result in extra low mask count for CMOS process integration. These excellent device characteristics, coupled with its simple processing, make the new device very promising for future large-area electronic applications.
  • Keywords
    CMOS integrated circuits; Schottky gate field effect transistors; leakage currents; semiconductor technology; thin film transistors; CMOS process integration; GIDL-like off-state leakage current; Schottky barrier thin-film transistor; ambipolar device operation; bias polarity switching; carrier sheet; channel offset region; field-induced drain extension; implantless feature; large-area electronic applications; low mask count; metal field-plate; n-channel mode; on-off current ratio; p-channel mode; passivation oxide; silicided source/drain; Amorphous materials; CMOS process; Fabrication; Helium; Laboratories; Leakage current; MOSFET circuits; Passivation; Schottky barriers; Thin film transistors;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/55.915606
  • Filename
    915606