• DocumentCode
    1467382
  • Title

    A 400 K-transistor CMOS sea-of-gates array with continuous track allocation

  • Author

    Okabe, Masatomi ; Okuno, Yoshihiro ; Arakawa, Takahiko ; Tomioka, Ichiro ; Ohno, Takio ; Noda, Tomoyoshi ; Hatanaka, Masahiro ; Kuramitsu, Yoichi

  • Author_Institution
    LSI Res. & Dev. Lab., Mitsubishi Electr. Corp., Hyogo, Japan
  • Volume
    24
  • Issue
    5
  • fYear
    1989
  • fDate
    10/1/1989 12:00:00 AM
  • Firstpage
    1280
  • Lastpage
    1286
  • Abstract
    A 0.8- mu m CMOS sea-of-gates (SOG) array with first-level wiring channels perpendicular to transistor rows and 40 0K transistors is integrated on a 6*7-mm2 chip. Implementation of a 64-bit multiplier shows 60-percent gate utilization and density of 1410 G/mm2. The wiring length of the multiplier is 70 percent of that in a conventional SOG.
  • Keywords
    CMOS integrated circuits; VLSI; integrated circuit technology; logic arrays; 0.8 micron; 6 to 7 mm; 60 percent; 64 bit; CMOS; SOG; continuous track allocation; density; first-level wiring channels; gate utilization; sea-of-gates array; wiring length; Application specific integrated circuits; Helium; Large scale integration; Large-scale systems; Logic; MOSFETs; Macrocell networks; Research and development; Silicon; Wiring;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1989.572597
  • Filename
    572597
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1467382