DocumentCode
1468329
Title
Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores
Author
Lu, Shyue-Kung ; Huang, Shi-Yu ; Wu, Cheng-Wen ; Chen, Yin-Mou
Author_Institution
Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan
Volume
28
Issue
4
fYear
2011
Firstpage
88
Lastpage
97
Abstract
This article proposes a new approach for an FPGA-based emulation system for IC fault diagnosis that incorporates three speedup techniques: circuit partitioning, fault-injection elements (using a novel design), and a fault-injection scan chain. Experimental results in terms of hardware overhead and emulation time for ISCAS-85 benchmark circuits are compared with previous works to highlight the 33× speedup and 44% reduced overhead of this proposed system.
Keywords
fault diagnosis; field programmable gate arrays; integrated circuit testing; logic testing; FPGA-based emulation system; IC fault diagnosis; circuit partitioning; emulation-based diagnosis technique; fault-injection element; fault-injection scan chain; logic cores; Benchmark testing; Circuit faults; Emulation; Fault diagnosis; Field programmable gate arrays; Logic gates; circuit partitioning; design and test; fault emulation; fault injection; fault-injection scan chain; logic diagnosis;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2011.25
Filename
5728786
Link To Document