Analysis of leakage current and leakage power reduction during write operation in CMOS SRAM cell

Author

Khare, Kavita ; Kar, Rajib ; Mandal, Durbadal ; Ghoshal, Sakti Prasad

Author_Institution

Electron. & Commun. Eng. Dept., Nat. Inst. of Technol., Durgapur, India

fYear

2014

fDate

3-5 April 2014

Firstpage

523

Lastpage

527

Abstract

Leakage power is a major issue for short channel devices. As the technology is shrinking (i.e., 180nm, 90nm, 45nm. etc.) the leakage current is increasing very fast. So, several methods and techniques have been proposed for leakage reduction in CMOS digital integrated circuits. Leakage power dissipation has become a sizable proportion of the total power dissipation in integrated circuit. This paper demonstrates the ideas of 6T, 8T and 10T models with sleep transistors. This proposed SRAM cells give the advantages over basic 6T, 8T and 10T transistor models. The SRAM cell with sleep transistor shows better leakage reduction approach than stack approaches. Here in this paper Analog environment virtuoso (cadence) simulator is used for analysis of the power associated with CMOS SRAM cell for 180nm technology.

Keywords

CMOS memory circuits; SRAM chips; leakage currents; 10T transistor models; 6T transistor models; 8T transistor models; Analog environment Virtuoso cadence; CMOS SRAM cell; CMOS digital integrated circuits; leakage current; leakage power reduction; size 180 nm; size 45 nm; size 90 nm; sleep transistors; write operation; CMOS integrated circuits; Integrated circuit modeling; Load modeling; SRAM cells; Switching circuits; Transistors; 6T-SRAM cell; 8T and 10T transistor models; Leakage current and leakage power; Proposed 6T; Sub-threshold leakage reduction;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Signal Processing (ICCSP), 2014 International Conference on

Conference_Location

Melmaruvathur

Print_ISBN

978-1-4799-3357-0

Type

conf

DOI

10.1109/ICCSP.2014.6949897

Filename

6949897