• DocumentCode
    1468981
  • Title

    On determining sensitization criterion in an iterative gate sizing process

  • Author

    Lin, How-Rern ; Hwang, Ting Ting

  • Author_Institution
    Dept. of Comput. Sci. & Inf. Eng., Da Yeh Univ., Changhua, Taiwan
  • Volume
    18
  • Issue
    2
  • fYear
    1999
  • fDate
    2/1/1999 12:00:00 AM
  • Firstpage
    231
  • Lastpage
    238
  • Abstract
    Since only sensitizable paths contribute to the delay of a circuit, false paths must be excluded in optimizing the delay of the circuit. However, just identifying sensitizable paths in the first place is not sufficient since during the optimization process, false paths may become sensitizable, and sensitizable paths false. In addition, some paths may shuttle frequently as false paths and sensitizable ones. That is, a thrashing phenomenon may occur. To lessen the thrashing phenomenon of critical paths, a loose sensitization criterion is proposed in this paper to identify both exact sensitizable paths and shuttle paths. Moreover, the selection of sensitization criterion should be related to the specified delay constraint of a given circuit. Taking into account the tightness of sensitization criterion and delay constraint together, we define in this paper a thrashing coefficient which is used to guide the selection of sensitization criterion in the performance optimization process. Moreover, to save time for path sensitizability analysis in the optimization process, we find a special type of false paths, function-false paths, which can be put aside since they never become sensitizable during the process
  • Keywords
    circuit CAD; circuit optimisation; combinational circuits; delays; integrated logic circuits; iterative methods; logic CAD; logic gates; delay constraint; delay optimization; function-false paths; iterative gate sizing process; performance optimization process; sensitizable paths; sensitization criterion determination; shuttle paths; thrashing phenomenon; Circuits; Computer science; Delay; Inverters; Iterative methods; Logic; Optimization; Performance analysis;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.743742
  • Filename
    743742