DocumentCode
1468993
Title
Exterior templates for capacitance computations [interconnections]
Author
Zemanian, Armen H. ; Chang, Victor A.
Author_Institution
Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
Volume
18
Issue
2
fYear
1999
fDate
2/1/1999 12:00:00 AM
Firstpage
248
Lastpage
251
Abstract
The computation of the capacitance coefficients for alternative interconnect configurations requiring repeated calculations as the configurations are changed can be substantially accelerated by using an “exterior template”, that is, a set of “template capacitors” connected to the surface of the smallest rectangular region encompassing the planned interconnects. These template capacitors represent the effect of the medium for the fringing field outside the rectangle, and they eliminate the need to sample the fringing field every time a new calculation is made. The template capacitors can be determined by using the theory of infinite grids to eliminate almost entirely the medium-truncation error. All this works for both two-dimensional and three-dimensional (3-D) configurations, and it is especially advantageous in the 3-D case
Keywords
VLSI; capacitance; electronic engineering computing; integrated circuit design; integrated circuit interconnections; 3D configuration; 3D configurations; alternative interconnect configurations; capacitance coefficients; capacitance computations; exterior templates; fringing field; infinite grids theory; medium-truncation error elimination; template capacitors; three-dimensional configurations; two-dimensional configurations; Acceleration; Capacitance; Capacitors; Finite difference methods; Grid computing; Integrated circuit interconnections; Sampling methods; Very large scale integration; Wires; Wiring;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.743747
Filename
743747
Link To Document