DocumentCode
1469082
Title
ORION 2.0: A Power-Area Simulator for Interconnection Networks
Author
Kahng, Andrew B. ; Li, Bin ; Peh, Li-Shiuan ; Samadi, Kambiz
Author_Institution
Depts. of Comput. Sci. & Eng., Univ. of California at San Diego, La Jolla, CA, USA
Volume
20
Issue
1
fYear
2012
Firstpage
191
Lastpage
196
Abstract
As industry moves towards multicore chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power has become crucially important. In this work, we present ORION 2.0, an enhanced NoC power and area simulator, which offers significant accuracy improvement relative to its predecessor, ORION 1.0.
Keywords
integrated circuit design; integrated circuit interconnections; network-on-chip; NoC power; ORION 2.0; early-stage estimation; first-order design constraint; interconnection networks; multicore chips; networks-on-chip; power-area simulator; scalable fabric; Clocks; Estimation; Integrated circuit modeling; Logic gates; Mathematical model; Switches; Transistors; Architectural-level modeling; design space exploration; network-on-chip (NoC);
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2010.2091686
Filename
5728901
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