Investigation of Back-Bias Capacitance Coupling Coefficient Measurement Methodology for Floating-Gate Nonvolatile Memory Cells

In this paper, we give a thorough investigation of a new capacitance coupling coefficient measurement methodology (a back-bias method) that extracts the gate capacitance coefficient of floating-gate memory cells. This measurement methodology that utilizes simple current-voltage measurements presents several advantages over current methodologies. It includes a figure of merit for determining the matching performance of a reference transistor to a memory cell, which plays a crucial role for the extraction of the correct gate coupling coefficient value. By this means, we investigate, for the first time, the impact of structural differences between a reference transistor and a memory cell on the gate coupling coefficient extraction. The back-bias method is compared with commonly used gate coupling coefficient extraction methods, and it is shown that it has a smaller extraction error for nonmatching reference transistors and memory cell pairs. Furthermore, it is demonstrated how the gate coupling coefficient extraction can be corrected if matching reference and memory cell structures cannot be found.