DocumentCode
1470453
Title
CMOS quaternary latch
Author
Current, K.W.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Davis, CA, USA
Volume
25
Issue
13
fYear
1989
fDate
6/22/1989 12:00:00 AM
Firstpage
856
Lastpage
858
Abstract
A new CMOS current-mode quaternary threshold logic latch circuit is presented. This circuit accepts and requantises quaternary logical currents during a SETUP clock mode and latches the input value during the HOLD clock mode. Using logical current increments of 10 mu A, the quaternary latch has been simulated to have a worst-case, three logic level transition, total SETUP and HOLD time of about 40 ns, and single level transition total SETUP and HOLD time of about 10 ns.
Keywords
CMOS integrated circuits; VLSI; flip-flops; integrated logic circuits; many-valued logics; threshold logic; 10 ns; 40 ns; CMOS quaternary latch; HOLD clock mode; HOLD time; SETUP clock mode; VLSI compatible; current mode CMOS; current-mode quaternary threshold logic latch; logical current increments; multiple valued logic; requantises quaternary logical currents; single level transition; three logic level transition;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19890577
Filename
91804
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