Single-Crystalline Si STacked ARray (STAR) NAND Flash Memory

Author

Yun, Jang-Gn ; Kim, Garam ; Lee, Joung-Eob ; Kim, Yoon ; Shim, Won Bo ; Lee, Jong-Ho ; Shin, Hyungcheol ; Lee, Jong Duk ; Park, Byung-Gook

Author_Institution

Semicond. R&D Center, Samsung Electron. Co. Ltd., Suwon, South Korea

Volume

58

Issue

4

fYear

2011

fDate

4/1/2011 12:00:00 AM

Firstpage

1006

Lastpage

1014

Abstract

In this paper, a 3-D NAND Flash memory array having multiple single-crystal Si nanowires is investigated. Device structure and fabrication process are described including the electrical isolation of stacked nanowires. Numerical simulation results focused on NAND Flash memory operation are delivered. Devices and array with stacked bit lines are fabricated, and memory characteristics such as program/erase select gate operation are measured. Array scheme is also discussed for the high-density bit-cost scalable 3-D stacked bit-line NAND Flash memory application.

Keywords

NAND circuits; elemental semiconductors; flash memories; nanowires; semiconductor growth; silicon; 3D NAND Flash memory array; STAR NAND flash memory; silicon nanowires; single-crystalline silicon stacked array; Arrays; Flash memory; Logic gates; Nanowires; Silicon; Silicon germanium; Damascene gate process; layer replacement and single-crystal Si nanowire; nand Flash memory; stacked bit lines; three-dimensional (3-D) memory;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2011.2107557

Filename

5729801