A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector

Author

Savoj, Jafar ; Razavi, Behzad

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

Volume

36

Issue

5

fYear

2001

fDate

5/1/2001 12:00:00 AM

Firstpage

761

Lastpage

768

Abstract

A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-μm CMOS technology in an area of 1.1×0.9 mm², the circuit exhibits an RMS jitter of 1 ps, a peak-to-peak jitter of 14.5 ps in the recovered clock, and a bit-error rate of 1.28×10^-6, with random data input of length 2²³-1. The power dissipation is 72 mW from a 2.5-V supply

Keywords

CMOS integrated circuits; demultiplexing; phase detectors; synchronisation; timing jitter; voltage-controlled oscillators; 0.18 micron; 10 Gbit/s; 2.5 V; 72 mW; RMS jitter; bit-error rate; clock and data recovery circuit; demultiplexing; half-rate linear phase detector; interpolating voltage-controlled oscillator; linear characteristic; peak-to-peak jitter; power dissipation; random data input; retiming; systematic phase offset; Bit error rate; CMOS technology; Circuits; Clocks; Demultiplexing; Detectors; Jitter; Phase detection; Power dissipation; Voltage-controlled oscillators;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.918913

Filename

918913