A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique

Author

Lee, Kyeongho ; Park, Joonbae ; Lee, Jeong-Woo ; Lee, Seung-Wook ; Huh, Hyung Ki ; Jeong, Deog-Kyoon ; Kim, Wonchan

Author_Institution

Global Commun. Technol., Santa Clara, CA, USA

Volume

36

Issue

5

fYear

2001

fDate

5/1/2001 12:00:00 AM

Firstpage

800

Lastpage

809

Abstract

A single-chip direct-conversion CMOS receiver for 2.4-GHz wide-band code-division multiple-access wireless local loop (WLL) is described. The chip includes a low noise amplifier, a 12-phase downconverter, a variable gain amplifier, a g_m-C channel selection filter, a programmable phase-locked loop for seven channel frequencies, and a 4-bit flash analog-to-digital converter. The proposed multiphase reduced frequency conversion scheme combined with a multiphase sampling fractional-N prescaler, a cascaded dc-offset canceler and distributed automatic gain control loops offers solutions to problems of a direct-conversion receiver. Experimental results show -115-dBm sensitivity, 4.4-dB noise figure, and 95-dB dynamic range, which sufficiently meet commercial WLL specification

Keywords

CMOS analogue integrated circuits; UHF frequency convertors; UHF integrated circuits; code division multiple access; radio access networks; radio receivers; 2.4 GHz; 4.4 dB; RF communication system; fractional-N frequency synthesizer; g_m-C filter; mixer; multiphase reduced frequency conversion; phase-locked loop; single-chip direct-conversion CMOS receiver; wide-band code-division multiple-access; wireless local loop; Analog-digital conversion; Broadband amplifiers; Filters; Frequency conversion; Gain; Low-noise amplifiers; Multiaccess communication; Phase locked loops; Phase noise; Wideband;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.918918

Filename

918918