A low-power 64-point pipeline FFT/IFFT processor for OFDM applications

Author

Yu, Chu ; Yen, Mao-Hsu ; Hsiung, Pao-Ann ; Chen, Sao-Jie

Author_Institution

Dept. of Electron. Eng., Nat. Ilan Univ., Yilan, Taiwan

Volume

57

Issue

1

fYear

2011

fDate

2/1/2011 12:00:00 AM

Firstpage

40

Lastpage

40

Abstract

4G and other wireless systems are currently hot topics of research and development in the communication field. Broadband wireless systems based on orthogonal frequency division multiplexing (OFDM) often require an inverse fast Fourier transform (IFFT) to produce multiple subcarriers. In this paper, we present the efficient implementation of a pipeline FFT/IFFT processor for OFDM applications. Our design adopts a single-path delay feedback style as the proposed hardware architecture. To eliminate the read-only memories (ROM´s) used to store the twiddle factors, the proposed architecture applies a reconfigurable complex multiplier and bit-parallel multipliers to achieve a ROM-less FFT/IFFT processor, thus consuming lower power than the existing works. The design spends about 33.6K gates, and its power consumption is about 9.8mW at 20MHz.

Keywords

4G mobile communication; OFDM modulation; broadband networks; fast Fourier transforms; low-power electronics; 4G communication; OFDM; ROM-less FFT/IFFT processor; bit-parallel multipliers; broadband wireless systems; frequency 20 MHz; inverse fast Fourier transform; low-power 64-point pipeline FFT/IFFT processor; multiple subcarriers; orthogonal frequency division multiplexing; power consumption; reconfigurable complex multiplier; single-path delay feedback; twiddle factors; Computer architecture; Discrete Fourier transforms; Hardware; OFDM; Pipelines; Power demand; Read only memory; FFT; IFFT; OFDM; complex multiplier;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/TCE.2011.5735479

Filename

5735479