Equivalence of clock gating and synchronization with applicability to GALS communication

Pausible clocking is a very popular approach for clock domain interfacing in GALS systems. However, accuracy and stability of the ring oscillator that is central to this principle are bad. This suggests to use gated crystal oscillators instead. In this paper we will formally show that the problem of clock gating is equivalent to the synchronization problem. We will present a fundamental block diagram for a gated clock, comprising an AND gate and a synchronizer for the control input, and will give evidence that the related circuits proposed so far in the literature are instantiations of this principle. According to our equivalence proof none of these circuits can hence be free from a residual risk of metastability; typically the MTBF is determined by the synchronizer block. This stands in contrast to the pausible clocking where the arbiter can safely prevent metastable outputs. We further argue that a handshake based data transfer (without clock stopping) yields essentially the same properties wrt. MTBF and performance, while causing more localized effects in case of a metastable upset. In conclusion the use of clock gating does not seem to provide any advantages over the alternative schemes and can hence not be recommended.