• DocumentCode
    1479266
  • Title

    Two novel multiway circuit partitioning algorithms using relaxed locking

  • Author

    Dasdan, Ali ; Aykanat, Cevdet

  • Author_Institution
    Dept. of Comput. Eng. & Inf. Sci., Bilkent Univ., Ankara, Turkey
  • Volume
    16
  • Issue
    2
  • fYear
    1997
  • fDate
    2/1/1997 12:00:00 AM
  • Firstpage
    169
  • Lastpage
    178
  • Abstract
    All the previous Kernighan-Lin-based (KL-based) circuit partitioning algorithms employ the locking mechanism, which enforces each cell to move exactly once per pass. In this paper, we propose two novel approaches for multiway circuit partitioning to overcome this limitation. Our approaches allow each cell to move more than once. Our first approach still uses the locking mechanism but in a relaxed way. It introduces the phase concept such that each pass can include more than one phase, and a phase can include at most one move of each cell. Our second approach does not use the locking mechanism at all. It introduces the mobility concept such that each cell can move as freely as allowed by its mobility. Each approach leads to KL-based generic algorithms whose parameters can be set to obtain algorithms with different performance characteristics. We generated three versions of each generic algorithm and evaluated them on a subset of common benchmark circuits in comparison with Sanchis´ algorithm (FMS) and the simulated annealing algorithm (SA). Experimental results show that our algorithms are efficient, they outperform FMS significantly, and they perform comparably to SA. Our algorithms perform relatively better as the number of parts in the partition increases as well as the density of the circuit decreases. This paper also provides guidelines for good parameter settings for the generic algorithms
  • Keywords
    VLSI; circuit layout CAD; computational complexity; genetic algorithms; integrated circuit layout; KL-based generic algorithms; Kernighan-Lin-based algorithms; VLSI layout; locking mechanism; mobility concept; multiway circuit partitioning algorithms; parameter settings; relaxed locking; Circuit simulation; Data structures; Flexible manufacturing systems; Guidelines; Information science; Integrated circuit interconnections; Iterative algorithms; Partitioning algorithms; Simulated annealing; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.573831
  • Filename
    573831