DocumentCode
1479357
Title
Low-voltage CMOS low-noise amplifier using planar-interleaved transformer
Author
Tang, Chih-Chun ; Liu, Shen-Iuan
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
37
Issue
8
fYear
2001
fDate
4/12/2001 12:00:00 AM
Firstpage
497
Lastpage
498
Abstract
A low-voltage CMOS low-noise amplifier (LNA) architecture is presented. A planar-interleaved transformer is used to couple the RF signal between cascode transistors in a conventional LNA topology. Based on the modified RF MOS model, a 5.2 GHz CMOS LNA with fully on-chip input/output matching was designed to verify the low-voltage LNA architecture. The measurement results show that it can be operated with 1 V supply voltage
Keywords
CMOS analogue integrated circuits; MMIC amplifiers; field effect MMIC; impedance matching; integrated circuit noise; low-power electronics; 1 V; 5.2 GHz; CMOS; LNA topology; RF MOS model; cascode transistors; fully on-chip input/output matching; low-noise amplifier; low-voltage electronics; planar-interleaved transformer;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20010366
Filename
919982
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