DocumentCode
1480749
Title
Statistical Evaluation of Process Damage Using an Arrayed Test Pattern in a Large Number of MOSFETs
Author
Watabe, Shunichi ; Teramoto, Akinobu ; Abe, Kenichi ; Fujisawa, Takafumi ; Miyamoto, Naoto ; Sugawa, Shigetoshi ; Ohmi, Tadahiro
Author_Institution
Grad. Sch. of Eng., Tohoku Univ., Sendai, Japan
Volume
57
Issue
6
fYear
2010
fDate
6/1/2010 12:00:00 AM
Firstpage
1310
Lastpage
1318
Abstract
Evaluating the statistical variations of MOSFETs is important for realizing accurate analog circuits and large-scale-integration devices. A new evaluation method for the statistical variation of the electrical characteristics of MOSFETs is presented. We have developed a test circuit for understanding the statistical and local variations of MOSFETs in a very short time. We demonstrate that the electrical characteristics in more than one million MOSFETs, such as the threshold voltage and the subthreshold swing (S-Factor), are measured in 30 min and that the measured results are very efficient in developing the fabrication process, the process equipment, and the device structure to reduce the statistical and local characteristic variation.
Keywords
MOSFET; semiconductor device testing; statistical analysis; MOSFET; S-factor; analog circuits; arrayed test pattern; electrical characteristics; fabrication process; large-scale-integration devices; process damage statistical variation evaluation; subthreshold swing; test circuit; threshold voltage; Circuit testing; Electric variables; Electric variables measurement; Energy consumption; Impurities; Insulation; MOSFETs; Plasma measurements; Silicon; Threshold voltage; Fluctuation; metal–oxide–silicon field-effect transistor (MOSFET); plasma damage; statistical evaluation; test structure; variation;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2010.2046080
Filename
5456150
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