Regular VLSI architectures for multiplication modulo (2n+1)

The authors describe VLSI architectures for multiplication modulo p, where p is a Fermat prime. With increasing p , ROM-based table lookup methods become unattractive for integration due to excessive memory requirements. Three novel methods are discussed and compared to ROM implementations with regard to their speed and complexity characteristics. The first method is based on an ( n+1)×(n+1)-bit array multiplier, the second on modulo p carry-save addition, and the third on modulo (p -1) carry-save addition using a bit-pair recoding scheme. All allow very high throughputs in pipelined implementations. While the former is very convenient for CAD (computer-aided design) environments providing a pipelined multiplier macrocell, the latter two are well-suited to full-custom implementation