High-density central I/O circuits for CMOS

Author

Masleid, Robert P.

Author_Institution

IBM Adv. Workstation. Div., Austin, TX, USA

Volume

26

Issue

3

fYear

1991

fDate

3/1/1991 12:00:00 AM

Firstpage

431

Lastpage

435

Abstract

An I/O circuit design for VLSI CMOS is described that reduced the percentage of chip area occupied by I/O circuits from roughly 22% to under 3% for a 256 I/O chip. The technique, implemented in the IBM RISC System/6000 workstation processor chips, uses stackable macros to improve density per I/O signal by 10 times. The reorganization of the I/O structure relies on a top layer of metal dedicated to I/O circuit-to-pad wiring and power distribution. It takes full advantage of C4 solder bond package connection technology, which allows package connections to be located over chip circuitry. Decoupling I/O circuit layout from package connection layout and grouping by identical circuit type permits the full range of layout optimization techniques to be applied. I/O circuits are produced that are fully compatible with internal circuit terrain

Keywords

CMOS integrated circuits; VLSI; buffer circuits; driver circuits; C4 solder bond; IBM RISC System/6000; VLSI CMOS; central I/O circuits; circuit-to-pad wiring; dedicated metal layer; layout optimization techniques; package connection technology; power distribution; stackable macros; workstation processor chips; Bonding; Ceramics; Circuit synthesis; Packaging; Protection; Reduced instruction set computing; Signal processing; Temperature; Very large scale integration; Workstations;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.75031

Filename

75031