Impact of surrounding gate transistor (SGT) for ultra-high-density LSI´s

Author

Takato, Hiroshi ; Sunouchi, Kazumasa ; Okabe, Naoko ; Nitayama, Akihiro ; Hieda, Katsuhiko ; Horiguchi, Fumio ; Masuoka, Fujio

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

38

Issue

3

fYear

1991

fDate

3/1/1991 12:00:00 AM

Firstpage

573

Lastpage

578

Abstract

A transistor with compact structures for future MOS devices is discussed. This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits. By using this transistor, the occupied area of the CMOS inverter can be shrunk to 50% of that using planar transistors. Other advantages, such as steep cutoff characteristics, very small substrate bias effects, and high reliability, are discussed. Its structure, which allows for the enlargement of gate-controllability to the channel and electric field relaxation at the drain edge, is described. The advantages of this SGT for large-scale integration (LSI) devices is discussed

Keywords

CMOS integrated circuits; VLSI; integrated circuit technology; integrated logic circuits; CMOS inverter; Si pillar island; ULSI; advantages; area reduction; compact structures; electric field relaxation; future MOS devices; gate electrode; gate electrode surrounds Si pillar; gate-controllability; high reliability; large-scale integration; occupied area; small substrate bias effects; steep cutoff characteristics; surrounding gate transistor; Circuits; Electrodes; Fabrication; Impurities; Large scale integration; MOS devices; Silicon; Threshold voltage; Transistors; Very large scale integration;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.75168

Filename

75168