A 12-b, 10-MHz, 250-mW CMOS A/D converter

Author

Ahn, Gil-Cho ; Choi, Hee-Cheol ; Lim, Shin-Il ; Lee, Seung-Hoon ; Lee, Chul-Dong

Author_Institution

Dept. of Electr. Eng., Sogang Univ., Seoul, South Korea

Volume

31

Issue

12

fYear

1996

fDate

12/1/1996 12:00:00 AM

Firstpage

2030

Lastpage

2035

Abstract

A 12-b, 10-MHz, 250-mW, four-stage analog-to-digital converter (ADC) was implemented using a 0.8-μm p-well CMOS technology. The ADC based on a digitally calibrated multiplying digital-to-analog converter (MDAC) selectively employs a binary-weighted capacitor array in the front-end stage and a unit-capacitor array in the remaining back-end stages to obtain 12 b level linearity while maintaining high yield. All the analog and digital circuit functional blocks are fully integrated on a single chip, which occupies a die area of 15 mm² (4.2 mm×3.6 mm). Measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the prototype are less than ±0.8 LSB and ±1.8 LSB, respectively

Keywords

CMOS integrated circuits; analogue-digital conversion; integrated circuit measurement; pipeline processing; 0.8 mum; 10 MHz; 12 bit; 250 mW; ADC; MDAC configuration; binary-weighted capacitor array; die area; differential nonlinearity; digitally calibrated multiplying digital-to-analog converter; four-stage analog-to-digital converter; high yield; integral nonlinearity; p-well CMOS technology; pipelined ADC architecture; unit-capacitor array; Analog-digital conversion; CMOS technology; Capacitors; Digital circuits; Digital-analog conversion; Integrated circuit measurements; Integrated circuit yield; Linearity; Prototypes; Semiconductor device measurement;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.545827

Filename

545827