Power dissipation and interconnect noise challenges in nanometer CMOS technologies

As CMOS technology continues to scale down, leakage currents and interconnection noise will become increasingly large due to the effects of electron tunnelling, short channel effects, coupling capacitance and other factors. Managing these factors by developing better circuits and processes is vital to the continuous success of CMOS technologies in the semiconductor industry. This would require innovative control techniques and architectures in all aspects of CMOS design. Architectural innovation has already lead to renewed industrial interests in asynchronous ICs, which using clockless structure, mitigate the effects of interconnect noise delays and other parasitics in circuits.