An algorithm for determining repetitive patterns in very large IC layouts

Author

Niewczas, Mariusz ; Maly, Wojciech ; Strojwas, Andrzej

Author_Institution

Dept. of Electron., Warsaw Univ. of Technol., Poland

Volume

18

Issue

4

fYear

1999

fDate

4/1/1999 12:00:00 AM

Firstpage

494

Lastpage

501

Abstract

This paper proposes an isometry invariant pattern matching algorithm tailored for layout-related processing of complex integrated circuit (IC) designs. This algorithm applies signatures identifying contour equivalence classes. The proposed algorithm is useful for data reduction purposes by enabling construction of a database of repeatable IC primitives. We show several results of analysis of the state-of-the-art IC´s which suggest that the diversity of patterns does not significantly increase with increasing chip size

Keywords

circuit layout CAD; data reduction; integrated circuit layout; pattern matching; complex integrated circuit designs; contour equivalence classes; data reduction; database; isometry invariant pattern matching algorithm; repeatable IC primitives; repetitive patterns determination algorithm; very large IC layouts; Algorithm design and analysis; Chemical technology; Design automation; Dictionaries; Integrated circuit interconnections; Integrated circuit layout; Pattern matching; Spatial databases; Stress; Surfaces;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.752932

Filename

752932