Multi-Slot Main Memory System for Post DDR3

This brief introduces a suitable architecture for a high-data rate and high-density system using bidirectional single-ended signaling. For chip-to-chip interconnections requiring high speed and high density for the main memory system, an SSTL-II-based structure was previously used. However, this structure is no longer applicable for higher speeds at higher densities. By using an optimum reflection coefficient at the junction of a branch, a multislot system acts in the same way as a point-to point system. This architecture significantly improves the signal integrity. The simulated jitter and eye openings, including transmission line loss, were improved by 53.4% for write operation and 65.1% for read operations at 3.2 Gbps under heavy loading conditions. The peak-to-peak time jitters of 67.1 and 72.0 ps were measured at 3.3 Gbps.