CVNS-Based Storage and Refreshing Scheme for a Multi-Valued Dynamic Memory

Author

Khodabandehloo, Golnar ; Mirhassani, Mitra ; Ahmadi, Majid

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Windsor, Windsor, ON, Canada

Volume

19

Issue

8

fYear

2011

Firstpage

1517

Lastpage

1521

Abstract

Multi-valued dynamic memories are appropriate for applications such as implementation of neural networks, where massive number of synaptic weights have to be stored on a chip. In this paper, a novel storage and refreshing configuration to store up to 4 bits (16 levels) per cell on a dynamic memory is proposed. This configuration is based on the Continuous Valued Number System (CVNS). Error correction method according to the CVNS properties is used in order to increase the noise margin of memory cells. Furthermore, by decreasing the leakage current, the refresh cycle time is increased. The circuits are designed, simulated, and finally laid out using 90-nm CMOS technology.

Keywords

CMOS memory circuits; circuit layout; circuit simulation; error correction; leakage currents; neural nets; storage management chips; CMOS technology; CVNS property; CVNS-based storage; circuit layout; circuit simulation; continuous valued number system; error correction method; leakage current; memory cells; multivalued dynamic memory; neural networks; noise margin; refresh cycle time; refreshing configuration; refreshing scheme; synaptic weights; CMOS memory circuits; CMOS technology; Circuit noise; Circuit simulation; Error correction; Error correction codes; Leakage current; Neural networks; Noise level; Random access memory; Continuous Valued Number System (CVNS); multi-valued memory; noise margin; refresh cycle time; storage cell;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2010.2048588

Filename

5463020