High-speed, highly sensitive OEIC using clocked vertical BJT´s photoDarlington in CMOS technology

Author

Ayadi, Kamel

Author_Institution

Semicond. Div., Siemens AG, Munich, Germany

Volume

34

Issue

4

fYear

1999

fDate

4/1/1999 12:00:00 AM

Firstpage

559

Lastpage

564

Abstract

A novel CMOS synchronized photoreceiver is proposed for conversion of optical input pulses to digital output signals. The photoreceiver circuit consists of a photoDarlington used as a detector of input light followed by a current-mirror comparator used as a converter to electronic signals. A combination of two p-n-p vertical CMOS bipolar junction transistors controlled by an external clock is designed to achieve the first clocked photoDarlington structure. The generated photocurrent is amplified and digitized by the current-mirror comparator in a return to-zero format. The synchronized photoreceiver has been implemented in a standard digital 0.7 μm, 5 V n-well CMOS technology with an effective area of 100×60 μm². It was measured to operate at 100 MHz with an external input light of 13.3 fJ/pulse (-18.8 dBm/beam)

Keywords

CMOS integrated circuits; high-speed integrated circuits; integrated optoelectronics; optical receivers; synchronisation; 0.7 micron; 100 MHz; 5 V; clocked photoDarlington structure; clocked vertical BJT photoDarlington; current-mirror comparator; digital output signals; high-speed OEIC; n-well CMOS technology; optical input pulses; p-n-p CMOS bipolar junction transistors; return to-zero format; synchronized photoreceiver; CMOS technology; Circuits; Clocks; High speed optical techniques; Optical pulses; Optical sensors; Optoelectronic devices; P-n junctions; Pulse measurements; Synchronization;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.753690

Filename

753690