Design of a high-throughput IDPC decoder for DVB-S2 using local memory banks

This paper proposes a novel LDPC (Low-Density Parity Check) decoder architecture to increase throughput for DVB-S2, a second generation standard of ETSI (European Telecommunications Standards Institute) for European satellite digital video broadcasting system, which is employed in European digital TVs. The proposed architecture clusters nodes of a Tanner graph into node groups utilizing the properties of IRA (Irregular Repeat-Accumulate) LDPC codes. Functional modules, which perform calculations for node groups, read and store messages at predetermined local memory banks. The memory banks are designed to avoid memory conflicts by differentiating read and store timings. Hence, throughput of the proposed architecture can be increased. Experimental results show that the throughput of the proposed architecture is increased by 104% ~ 479%, when compared to previous architectures.