Proposal of a partial-ground-plane (PGP) silicon-on-insulator (SOI) MOSFET for deep sub-0.1-μm channel regime

Author

Yanagi, S. ; Nakakubo, A. ; Omura, Y.

Author_Institution

Fac. of Eng., Kansai Univ., Osaka, Japan

Volume

22

Issue

6

fYear

2001

fDate

6/1/2001 12:00:00 AM

Firstpage

278

Lastpage

280

Abstract

This letter proposes a new device structure which is called the "partial-ground-plane (PGP) silicon-on-insulator (SOI) MOSFET." The PGP SOI MOSFET minimizes the short-channel effect (SCE) compared to the conventional single-gate (SG) SOI MOSFET because the gate-induced field in the SOI layer is held high by the PGP region. This results in a lower stand-by leakage current. The PGP SOI MOSFET also shows much better switching performance and extremely high analog performance because of its smaller parasitic capacitance compared to the conventional ground-plane (GP) device. Thus, it is shown that the PGP SOI MOSFET is a promising candidate for future deep-sub-0.1-μm mixed-mode LSIs.

Keywords

CMOS analogue integrated circuits; MOSFET; leakage currents; mixed analogue-digital integrated circuits; silicon-on-insulator; 0.05 to 0.3 mum; Si-SiO/sub 2/; deep sub-0.1-/spl mu/m channel regime; extremely high analog performance; gate-induced field; mixed-mode LSIs; parasitic capacitance; partial-ground-plane SOI MOSFET; short-channel effect; stand-by leakage current; switching performance; Electrodes; Large scale integration; Leakage current; MOSFET circuits; Parasitic capacitance; Proposals; Resists; Silicon on insulator technology; Size control; Threshold voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.924841

Filename

924841