DocumentCode
1494682
Title
Compact test generation for full scan sequential circuits using multiple frame vectors
Author
Dong Ho Lee
Author_Institution
Sch. of Electron. & Electr. Eng., Kyungpook Nat. Univ., Taegu
Volume
35
Issue
3
fYear
1999
fDate
2/4/1999 12:00:00 AM
Firstpage
182
Lastpage
183
Abstract
A new test set compaction method that uses multiple frame vectors to test fully scanned sequential circuits is proposed. The FAN algorithm is extended to generate compact multiple frame test vectors. The proposed method generates the smallest test sets among all recognised full scan test set compaction algorithms
Keywords
logic testing; sequential circuits; FAN algorithm; compaction algorithm; full scan sequential circuit; multiple frame vectors; test generation;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19990145
Filename
755903
Link To Document