The compiled logic simulator

Author

Keller, Brion T. ; Carlson, David P. ; Maloney, William B.

Author_Institution

IBM Corp., Endicott, NY, USA

Volume

8

Issue

1

fYear

1991

fDate

3/1/1991 12:00:00 AM

Firstpage

21

Lastpage

34

Abstract

A two-value, zero-delay simulator that computes signatures and analyzes fault coverage for circuits with built-in self-test (BIST) is described. The simulator, called the compiled logic simulator (CLS), is used with a monitor that simulates BIST control logic at a high level. The simulator´s compiled code is well suited to the IBM 3090 pipeline and fault simulation using flat random patterns. The linear-feedback-shift-register simulation monitor is discussed. Performance results are presented. Fault simulation with one million random patterns on a 40000-gate circuit was done in 16 CPU minutes.<>

Keywords

built-in self test; circuit analysis computing; feedback; logic CAD; logic testing; shift registers; IBM 3090 pipeline; built-in self-test; compiled logic simulator; fault coverage; fault simulation; flat random patterns; linear-feedback-shift-register simulation monitor; random patterns; signature analysis; two-value simulator; zero-delay simulator; Analytical models; Built-in self-test; Central Processing Unit; Circuit analysis computing; Circuit faults; Circuit simulation; Computational modeling; Logic; Monitoring; Pipelines;

fLanguage

English

Journal_Title

Design & Test of Computers, IEEE

Publisher

ieee

ISSN

0740-7475

Type

jour

DOI

10.1109/54.75660

Filename

75660