Modeling Interrupts for Software-Based System-on-Chip Verification

The interrupt mechanism in a system-on-chip (SoC) joins the SoCs hardware and software behaviors. We model interrupts as logical rather than physical events and accordingly provides guidelines to compose software components including interrupt-service-routines. As a benefit, classical indeterministic behaviors (due to the parallelism) in the software domain, such as preemption and nesting, can be constructed as early as raw hardware components are being integrated. In effect, while the interrupt mechanism itself is under rigorous stress, it is simultaneously driving the exercise of the entire SoC. This effect can be observed through software profiling at the hardware integration stage.