A two-level interleaving architecture for serial convolvers

Author

Marino, Francescomaria

Author_Institution

Dipt. di Elettrotecnica ed Eletron., Politecnico di Bari, Italy

Volume

47

Issue

5

fYear

1999

fDate

5/1/1999 12:00:00 AM

Firstpage

1481

Lastpage

1486

Abstract

We present a bit-serial architecture for convolving/correlating long numerical sequences by long filter functions. Because of its two-level interleaving structure, the proposed device does not require “wait cycles” between consecutive input samples. As a result, it achieves the highest possible throughput. Cascadability, fault tolerance, feasibility in VLSI technology, and computing performances are discussed and analyzed

Keywords

CMOS digital integrated circuits; VLSI; convolution; correlators; digital signal processing chips; fault tolerance; parallel architectures; pipeline arithmetic; sequences; CMOS; VLSI technology; bit-serial architecture; cascadability; computing performance; correlation; fault tolerance; input samples; long filter functions; long numerical sequences; pipelining; serial convolvers; serial/parallel multiplier; throughput; two-level interleaving architecture; Computer architecture; Convolvers; Diffraction; Fourier transforms; Interleaved codes; Performance analysis; Scattering; Shape measurement; Signal processing; Tomography;

fLanguage

English

Journal_Title

Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1053-587X

Type

jour

DOI

10.1109/78.757248

Filename

757248