Temperature-stable voltage reference based on different threshold voltages of NMOS transistors

A temperature-stable voltage reference based on threshold voltages of enhancement and depletion NMOS transistors has been presented and implemented with a 0.5 mum DPDM CMOS technology. The problem of a fixed voltage reference value is avoided by different parameter design. A significant reduce of temperature dependence of mobility is also achieved. The chip s area is 0.014 mm². The test results show that the operation supply voltage is from 2 to 5 V, the maximum supply current is 8.24 muA, and the average reference voltage is 765 mV with an average line regulation of plusmn0.187%/V. A typical temperature coefficient of 39.2 ppm/degC for a temperature range of 0-100degC is obtained. The power-supply rejection ratio, without any filtering capacitors, is -46 dB at 100 Hz and -32 dB at 1 MHz for the smallest supply voltage.