An Efficient Multimode Multiplier Supporting AES and Fundamental Operations of Public-Key Cryptosystems

Author

Wang, Chen-Hsing ; Chuang, Chieh-Lin ; Wu, Cheng-Wen

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

Volume

18

Issue

4

fYear

2010

fDate

4/1/2010 12:00:00 AM

Firstpage

553

Lastpage

563

Abstract

This paper presents a highly efficient multimode multiplier supporting prime field, namely, polynomial field, and matrix-vector multiplications based on an asymmetric word-based Montgomery multiplication (MM) algorithm. The proposed multimode 128 ?? 32 b multiplier provides throughput rates of 441 and 511 Mb/s for 256-b operands over GF(P) and GF(2ⁿ) at a clock rate of 100 MHz, respectively. With 21 930 additional gates for Advanced Encryption Standard (AES), the multiplier is extended to provide 1.28-, 1.06-, and 0.91-Gb/s throughput rates for 128-, 192-, and 256-b keys, respectively. The comparison result shows that the proposed integration architecture outperforms others in terms of performance and efficiency for both AES and MM that is essential in most public-key cryptosystems.

Keywords

matrix multiplication; public key cryptography; advanced encryption standard; asymmetric word-based Montgomery multiplication algorithm; digital signal algorithm; elliptic curve cryptography; matrix-vector multiplications; multimode multiplier; polynomial field; public-key cryptosystems; Advanced Encryption Standard (AES); Elliptic-curve cryptography (ECC); Montgomery multiplication (MM); Rivest, Shamir, and Adleman (RSA); composite field arithmetic; digital signal algorithm (DSA);

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2009.2013958

Filename

5288547